In a conventional semiconductor device, a chip is attached to a chip carrier such as a lead frame or a substrate and is electrically connected to the chip carrier by a plurality of bonding wires where the chip carrier has a plurality of bonding fingers for wire-bonding. However, as the development of higher circuit densities, finer pad pitches, and smaller package dimensions, the width and the spacing between the bonding fingers become smaller and smaller leading to easily electrical short between bonding wires and adjacent fingers. Furthermore, the allowable spacing on a bonding finger for cutting wires also become smaller and smaller leading to difficulties of wire bonding. The existing solution is to specially design an exclusive chip carrier where its bonding fingers are arranged corresponding to the bonding pads of a chip with specific dimensions or with specific bonding pad layouts. Therefore, the chip carrier only can be used for one specific IC chip leading to higher packaging costs.
As shown in FIG. 1 and FIG. 2, a conventional semiconductor device 100 primarily comprises a plurality of first leads 110 and a plurality of second leads 150 made of a same leadframe, a chip 120, and a plurality of first bonding wires 131 and second bonding wires 132. Parts of the first leads 110 and the second leads 150 in the semiconductor device 100 are called internal leads including a plurality of bonding fingers 111 and 151 for wire bonding, respectively. The first leads 110 and the second leads 150 have a plurality of external leads extended from two opposing sides of the semiconductor device 100 respectively. As shown in FIG. 2 again, the bonding fingers 111 of the first leads 110 and the bonding fingers 151 of the second leads 150 are arranged in parallel and are divided from a spacing line S1 where the internal ends of the first lead 110 and the internal ends of the second leads 150 are disposed at two opposing sides of the spacing line S1. The length of the first lead 110 is longer than the one of the second lead 150 for disposing the chip 120. Some of the bonding pads 122 of the chip 120 are electrically connected to the bonding fingers 111 of the first leads 110 by the first bonding wires 131 and the other of the bonding pads 122 of the chip 120 are electrically connected to the bonding fingers 151 of the second leads 150 by the second bonding wires 132. The encapsulant 170 encapsulates the chip 120, the first bonding wires 131, the second bonding wires 132, the internal leads of the first leads 110 and the second leads 150 with the external leads of the first leads 110 and the second leads 150 exposed from two opposing sides of the encapsulant 170. As shown in FIG. 2, the layout of the bonding fingers 111 of the first leads 110 and the layout of the bonding fingers 151 of the second leads 150 are corresponding to the layout of the bonding pads 122 of the chip 120 to ensure the wire bonding directions of the first bonding wires 131 and the second bonding wires 132 are compliant to the extending directions of the bonding fingers 111 of the first leads 110 and the bonding fingers 151 of the second leads 150. Therefore, the semiconductor device 100 only can assemble a specific chip 120 with a specific chip dimension and a specific bonding pad layout as shown in FIG. 2. If a chip with different chip dimensions and/or with different bonding pad layouts are selected, the bonding wires are bonded to the fingers with a larger minimum angle even with cross wiring leading to easy electrical short with the adjacent bonding fingers or/and bonding wires during wire-bonding or molding processes.